Industry Knowledge Graph

The Bit-Watt Framework

Bit = compute density. Watt = power density. Where they intersect, coupling points form: nodes of disproportionate margin and structural moat. This wiki maps those nodes.

Bit

Information density across the compute stack: how much intelligence per unit of silicon, memory, and bandwidth.

  • Compute · GPU/TPU FLOPS density, MoE routing, quantization-native architectures
  • Storage · HBM capacity per package, KV cache compression, memory bandwidth per watt
  • Interconnect · NVLink, CoWoS interposer, chip-to-chip bandwidth, CPO

Watt

Power density across the energy stack: how much compute per unit of energy, from chip-level TDP to grid-level supply.

  • Chip power · TDP efficiency, dynamic voltage scaling, per-FLOP energy cost
  • Cooling · Liquid cooling density, PUE optimization, thermal management at rack level
  • Grid supply · Data center power contracts, SMR/fusion, renewable capacity

Coupling Point

When a Bit bottleneck and a Watt bottleneck intersect at the same supply-chain node, a coupling point forms. Companies that control coupling points earn disproportionate margins and create structural moats.

Bit constraint × Watt constraint = Alpha

Atlas Gallery

Interactive coupling-point maps

Each atlas applies the Bit-Watt framework to a specific supply chain. Interactive bubble charts, PE-border encoding, and company-level premium analysis.

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